A serializer/deserializer (also referred as SERDES) is usually used in high speed communications. By the SERDES architecture, a parallel data is converted into a serial data in a transmitting device, and the serial data is restored to the parallel data in a receiving device. The SERDES architectures are widely used in high-speed storage interface such as SATA interfaces, SAS (Serial SCSI) interfaces, USB 2.0/3.0 interfaces, PCI-e interfaces, HDMI interfaces, XAUI interfaces, 10G interfaces or fiber-optic interfaces.
FIG. 1 is a schematic functional block diagram illustrating a conventional SERDES architecture. For example, the conventional SERDES architecture is disclosed in U.S. Pat. No. 8,243,782. As shown in FIG. 1, the conventional SERDES architecture includes a transmitting device 61, a receiving device 65, and a channel 63. A serial data (in) is transmitted from a transmitter 61a of the transmitting device 61 to a receiver 65a of the receiving device 65 through the channel 63. In particular, after the serial data is equalized by a transmitter equalizer (Tx equalizer) 61b of the transmitter 61a, a transmitting signal is outputted. After the transmitting signal is transmitted through the channel 63, the transmitting signal is an input signal of the receiving device 65.
The receiver 65a of the receiving device 65 includes a receiver equalizer and sampler (RX equalizer and sampler) 651, a measuring circuit 653, and an adaptive controller 655. However, while the transmitting signal passes through the channel, the transmitting signal is usually affected by inter-symbol Interferences (ISI), insertion loss or return loss. Consequently, after a serial data (out) is recovered from the input signal by the RX equalizer and sampler 651, the serial data (out) has to be corrected according to the measured signal quality.
For evaluating the quality of the input signal, the equalized input signal is further measured by the measuring circuit 653 of the receiver 65a. The measuring result is transmitted from the measuring circuit 653 to the adaptive controller 655. According to the measuring result, the adaptive controller 655 will judge whether the settings of the receiving device 61 and the receiving device 65 have to be adjusted or not.
For example, if the measuring result from the measuring circuit 653 indicates that the quality of the input signal is unqualified, the adaptive controller 655 generates an adjusted signal. The adjusting signal is fed back to the RX equalizer and sampler 651 of the receiver 65a and the Tx equalizer 61b of the transmitter 61a. According to the adjusting signal, the settings of the RX equalizer and sampler 651 of the receiver 65a and the Tx equalizer 61b of the transmitter 61a are correspondingly adjusted.
After the settings of the RX equalizer and sampler 651 of the receiver 65a and the Tx equalizer 61b of the transmitter 61a are adjusted, a corresponding new input signal is measured by the measuring circuit 653, and a new measuring result is generated by the measuring circuit 653. Similarly, if the measuring result indicates that the quality of the input signal is unqualified, the adaptive controller 655 generates a new adjusted signal again. The new adjusting signal is fed back to the RX equalizer and sampler 651 of the receiver 65a and the Tx equalizer 61b of the transmitter 61a again. The above procedures are repeatedly done until the measuring result from the measuring circuit 653 indicates that the quality of the input signal is qualified.
Generally, the bit error rate (BER) is a parameter indicating the quality of a received signal of a system. According to many high-speed transmission standards, the bit error rate should be lower than an expectation value. For example, the allowable bit error rate of the SERDES system is lower than 10−12; and the allowable bit error rate of the fiber-optic system is lower than 10−15. In the SERDES architecture of FIG. 1, the input signal is repeatedly measured, the adjusting signal is repeatedly fed back to the transmitter 61a and the receiver 65a, and the settings of the transmitter 61a and the receiver 65a are repeatedly adjusted. Consequently, the quality of the input signal can meet the BER requirement.
However, it is necessary for the measuring circuit 653 to efficiently and accurately measure the quality of the input signal in order to meet the BER requirement. If the quality of the input signal is not efficiently and accurately measured, the process of adjusting the settings of the transmitter 61a and the receiver 65a is either inefficient or incorrect.